Job Title: Senior DFT Engineer
Location: UK (Oxford or Bristol)
Contract Type: Full-time, permanent position (Hybrid Working)

Salary: £50,000- £75,000

Summary:
My client is looking for an experienced Senior Design for Test (DFT) Engineer with specialist expertise in digital ASIC/SoC development. The successful candidate will have a strong academic background and extensive knowledge of DFT in complex ASIC/SoC designs, including power management, memories, and Analog IP elements.

This is an SME organisation with a high volume of projects available across a long list of industry sectors, including Medical, Automotive & Telecommunications.

Responsibilities:

Take full ownership of DFT, BIST, and test-pattern generation for complex digital and mixed-signal ASIC designs.
Offer consultancy on test-related issues to clients during pre-sales and implementation phases.
Configure, run, and maintain EDA tool flows related to DFT, BIST, and test pattern generation.
Collaborate with front-end and back-end teams to implement and verify DFT throughout the development process.
Ensure customer fault-coverage expectations and requirements are met.
Act as the primary contact between the company and any sub-contracted back-end service providers.
Create test specification documentation for sub-contractors providing test services.
Keep abreast of the latest ASIC Test methodologies and best practices to maintain up-to-date expertise and services.Key Skills / Experience:

Essential:

A 1st or 2.1 degree in Electronics, Physics, or a related field from a Tier 1 university.
5-10 years of industry experience with a proven track record in DFT across multiple successful ASIC projects.
Strong skills in DFT implementation, including:
Architectural specification
Tool-based and manual implementation
IP integration, including CPUs, Analog Macros, and IO PHYs
BIST and memory repair integration
Coverage analysis and improvement
ATPG, manual, and semi-automatic TPG, including simulation-based methods
At-speed test methodologies
DFT for power-managed designs
Generation of STA and scenario/mode constraints
Proficiency with a complete EDA vendor DFT tool suite (e.g., Siemens Tessent suite).
Knowledge of STA tools (e.g., Synopsys Primetime, Cadence Tempus) is a plus.
Experience with the complete SoC design flow and associated tools and methodologies.
Experience with RTL and gate-level simulations and related debugging for DFT verification.
VHDL/Verilog coding skills.
Experience working with test service providers, including test hardware and program specification, bring-up, and debug.Personality:

Excellent communication and interpersonal skills.
Strong presentation skills, capable of interacting with senior management.
Self-motivated with a strong customer service orientation and a 'can-do' attitude.
Creative problem-solving abilities.
Team player.
Ability to thrive in a dynamic environment.Position Specifics:

Flexible role with some UK and international travel required.
Applicants must have the right to live and work in the UK.